A patch is pending via x86/urgent to workaround an issue with Intel Alder Lake and Raptor Lake processors that is leaving the kernel developers for the time being to disable Process Context Identifiers (PCID) with these Intel mobile/desktop processors.
A patch is set to be mainlined for Linux 6.4 development and also back-ported to the stable kernel versions around avoiding incomplete global INVLPG flushes. The patch from an Intel Linux engineer explains:
“The INVLPG instruction is used to invalidate TLB entries for a specified virtual address. When PCIDs are enabled, INVLPG is supposed to invalidate TLB entries for the specified address for both the current PCID *and* Global entries. (Note: Only kernel mappings set Global=1.)
Unfortunately, some INVLPG implementations can leave Global translations unflushed when PCIDs are enabled.
As a workaround, never enable PCIDs on affected processors.
I expect there to eventually be microcode mitigations to replace this software workaround. However, the exact version numbers where that will happen are not known today. Once the version numbers are set in stone, the processor list can be tweaked to only disable PCIDs on affected processors with affected microcode.
Note: if anyone wants a quick fix that doesn’t require patching, just stick ‘nopcid’ on your kernel command-line.”
The affected processors end up being Intel Alder Lake and Raptor Lake processors. As mentioned in the patch message, Intel is said to be working on a microcode mitigation for this issue but for now at least the Linux kernel is set to disable PCID support for Alder Lake / Alder Lake L / Alder Lake N / Raptor Lake / Raptor Lake P / Raptor Lake S until the microcode mitigation can be handled.
INVLPG is used for invalidating specified TLB entries. At least Alder Lake and Raptor Lake don’t need Kernel Page Table Isolation (KPTI) for mitigating Meltdown since these newer processors are unaffected by it. But for older Intel processors, PCID support helped offset some of the overhead in dealing with Kernel Page Table Isolation / mitigating Meltdown as shown several years back. The kernel PTI documentation goes on to more extensively note the benefits of PCID support:
“Process Context IDentifiers (PCID) is a CPU feature that allows us to skip flushing the entire TLB when switching page tables by setting a special bit in CR3 when the page tables are changed. This makes switching the page tables (at context switch, or kernel entry/exit) cheaper. But, on systems with PCID support, the context switch code must flush both the user and kernel entries out of the TLB. The user PCID TLB flush is deferred until the exit to userspace, minimizing the cost. See intel.com/sdm for the gory PCID/INVPCID details.
On systems without PCID support, each CR3 write flushes the entire TLB. That means that each syscall, interrupt or exception flushes the TLB.”
In any event I’ll be running some benchmarks on Raptor Lake for seeing if this — at least temporary — disabling of PCID support means for any of the usual areas of performance for end-users.